In layout design of a semiconductor device including a memory circuit and a memory BIST circuit (self-diagnostic circuit) for testing the memory circuit, generally, the memory BIST circuit is arranged in a vicinity of the memory circuit so that timing is easily met in timing verification. As illustrated in FIG. 10A and FIG. 10B, an arrangement region 102 where unit cells can be placed is provided in a vicinity of a memory circuit 101, and unit cells which constitute a memory BIST circuit are arranged in the region 102.
In order to realize fast operation and reduction of a circuit area, there is a manner that a part of the memory BIST circuit is built in the memory circuit. For example, as illustrated in FIG. 11A, comparators (COMP.) of the memory BIST circuit which compare whether an expected value matches an output value of a memory circuit or not are built in the memory circuits. A BIST pattern generator (BPG) which performs generation of a test data pattern and execution control is arranged between the memory circuits. For example, as illustrated in FIG. 11B, the comparators (COMP.) of the memory BIST circuit are built in the memory circuits, and the BIST pattern generator (BPG) is arranged in a core region (normal logic circuit region) without setting a region where unit cells can be placed between the memory circuits. Further, Patent Documents 1 to 3 disclose examples of memory circuits in which memory BIST circuits are built.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2006-114785                [Patent Document 2] Japanese Laid-open Patent Publication No. 2000-111618        [Patent Document 3] Japanese Laid-open Patent Publication No. 11-316263        
Along with miniaturization of a semiconductor device, in reducing an area related to a memory BIST circuit, wiring congestion between memory circuits hinders reduction of a circuit area (chip area). For example, when the region where unit cells can be placed is set between memory circuits in order to arrange the memory BIST circuit in a vicinity of the memory circuit, wiring resource is used for supplying power to hinder the reduction of the circuit area (chip area).
As described above, in order to realize the fast operation and the reduction of the circuit area, there is a manner that the comparator of the memory BIST circuit is built in the memory circuit. However, in the case of such an arrangement as illustrated in FIG. 11A, in order to arrange the BIST pattern generator (BPG) of the memory BIST circuit between the memory circuits, the region where the unit cells can be placed is set. Therefore, for supplying power to the region where the unit cells can be placed set between the memory circuits, the wiring characteristic of the semiconductor device (chip) has been left impaired.
In the case of such an arrangement as illustrated in FIG. 11B, signal wiring from a system logic circuit and signal wiring of the memory BIST circuit concentrate, so that the wiring characteristic is poor. Further, since a distance between the BIST pattern generator (BPG) of the memory BIST circuit and the memory circuits subjected to a test increases, there is a problem that a timing adjustment at a time of testing at speed becomes difficult.
Further, the region where the unit cells can be placed is provided between the memory circuits, whereby a useless region occurs in a well in the semiconductor device. As illustrated in FIG. 12, intervals between wells 123 in a memory circuit 121 are determined by a pitch of memory cells in the memory circuit, but intervals between wells 124 in a region 122 where the unit cells can be placed are determined irrelevantly thereto. Therefore, in order to keep a design rule (prevention of a short circuit between wells), a certain interval 125 is provided between the wells 123 in the memory circuit 121 and the wells 124 in the region 122. Since the wells 123 in the memory circuit 121 and the wells 124 in the region 122 separate from each other, TAPs 126, 127 are provided on the wells 123, 124 respectively, resulting in increased area.